CY14B104NA-BA25IT 查看數據表（PDF） - Cypress Semiconductor
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CY14B104NA-BA25IT Datasheet PDF : 26 Pages
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CY14B104LA, CY14B104NA
AC Switching Characteristics
Over the Operating Range
Parameters [20]
Cypress
Parameter
Alt Parameter
Description
SRAM Read Cycle
tACE
tRC[21]
tAA[22]
tACS
tRC
tAA
tDOE
tOHA[22]
tLZCE[23, 24]
tHZCE[23, 24]
tLZOE[23, 24]
tHZOE[23, 24]
tPU[23]
tPD[23]
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
tDBE
–
tLZBE[23]
–
tHZBE[23]
–
SRAM Write Cycle
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
tWC
tWC
tPWE
tWP
tSCE
tCW
tSD
tDW
tHD
tDH
tAW
tAW
tSA
tAS
tHA
tWR
tHZWE[23, 24, 25] tWZ
tLZWE[23, 24]
tOW
tBW
–
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
20 ns
25 ns
45 ns
Min Max Min Max Min Max Unit
–
20
–
25
–
45 ns
20
–
25
–
45
–
ns
–
20
–
25
–
45 ns
–
10
–
12
–
20 ns
3
–
3
–
3
– ns
3
–
3
–
3
– ns
–
8
–
10
–
15 ns
0
–
0
–
0
– ns
–
8
–
10
–
15 ns
0
–
0
–
0
– ns
–
20
–
25
–
45 ns
–
10
–
12
–
20 ns
0
–
0
–
0
– ns
–
8
–
10
–
15 ns
20
–
25
–
45
–
ns
15
–
20
–
30
–
ns
15
–
20
–
30
–
ns
8
–
10
–
15
–
ns
0
–
0
–
0
– ns
15
–
20
–
30
–
ns
0
–
0
–
0
– ns
0
–
0
–
0
– ns
–
8
–
10
–
15 ns
3
–
3
–
3
– ns
15
–
20
–
30
–
ns
Switching Waveforms
Figure 6. SRAM Read Cycle #1 (Address Controlled) [21, 22, 26]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
20.
Test conditions assume signal transition time of
IOL/IOH and load capacitance shown in Figure 5
3 ns or less,
on page 10.
timing
reference
levels
of
VCC/2,
input
pulse
levels
of
0
to
VCC(typ),
and
output
loading
of
the
specified
21. WE must be HIGH during SRAM read cycles.
22. Device is continuously selected with CE, OE and BHE / BLE LOW.
23. These parameters are guaranteed by design but not tested.
24. Measured ±200 mV from steady state output voltage.
25. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
26. HSB must remain HIGH during read and write cycles.
Document Number: 001-49918 Rev. *L
Page 11 of 26
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