CY14B256KA-SP45XI 查看數據表（PDF） - Cypress Semiconductor

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CY14B256KA-SP45XI

256-Kbit (32 K × 8) nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B256KA

to ‘0’, the power fail monitor only affects the PF flag in flags

register.

High/Low (H/L). When set to a ‘1’, the INT pin is active HIGH

and the driver mode is push pull. The INT pin drives high only

when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin

is active LOW and the drive mode is open drain. The INT pin

must be pulled up to Vcc by a 10 k resistor while using the

interrupt in active LOW mode.

Pulse/Level (P/L). When set to a ‘1’ and an interrupt occurs, the

INT pin is driven for approximately 200 ms. When P/L is set to a

‘0’, the INT pin is driven high or low (determined by H/L) until the

flags register is read.

When an enabled interrupt source activates the INT pin, an

external host reads the flags register to determine the cause. All

flags are cleared when the register is read. If the INT pin is

programmed for level mode, then the condition clears and the

INT pin returns to its inactive state. If the pin is programmed for

pulse mode, then reading the flag also clears the flag and the pin.

The pulse does not complete its specified duration if the flags

register is read. If the INT pin is used as a host reset, then the

flags register is not read during a reset.

Flags Register

The flags register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. These flags are set by the watchdog

timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts to be informed

when a flag is set. These flags are automatically reset when the register is read. The flags register is automatically loaded with the

value 0x00 on power-up (except for the OSCF bit; see Stopping and Starting the Oscillator on page 8).

Figure 4. RTC Recommended Component Configuration [5]

Recommended Values

Y1 = 32.768 kHz (12.5 pF)

C1 = 10 pF

C2 = 67 pF

Note: The recommended values for C1 and C2 include

board trace capacitance.

C1

Y1

C2

Xout

Xin

Watchdog

Timer

Power

Monitor

VINT

Clock

Alarm

WDF

WIE

PF

PFE

AF

AIE

Figure 5. Interrupt Block Diagram

P/L

VCC

Pin

Driver

INT

H/L

VSS

WDF - Watchdog Timer Flag

WIE - Watchdog Interrupt

Enable

PF - Power Fail Flag

PFE - Power Fail Enable

AF - Alarm Flag

AIE - Alarm Interrupt Enable

P/L - Pulse Level

H/L - High/Low

Note

5. For nonvolatile static random access memory (nvSRAM) real time clock (RTC) design guidelines and best practices, see application note AN61546.

Document Number: 001-55720 Rev. *G

Page 10 of 27

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