CY14B256L(2007) 查看數據表（PDF） - Cypress Semiconductor

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CY14B256L
(Rev.:2007)

256-Kbit (32K x 8) nvSRAM

Cypress Semiconductor 

PRELIMINARY

Switching Waveforms

SRAM Read Cycle 1 (address controlled) [8, 9, 20]

CY14B256L

ADDRESS

DQ (DATA OUT)

tAA

tOHA

tRC

DATA VALID

SRAM Read Cycle 2 (CE controlled) [8, 20]

ADDRESS

CE

tRC

tLZCE

tACE

OE

DQ (DATA OUT)

ICC

tDOE

tLZOE

tPU

STANDBY

ACTIVE

tPD

tHZCE

tHZOE

DATA VALID

Note

20. HSB must remain HIGH during READ and WRITE cycles.

Document #: 001-06422 Rev. *E

Page 11 of 17

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