CY14B256Q3(2013) 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY14B256Q3
(Rev.:2013)

256-Kbit (32 K × 8) Serial (SPI) nvSRAM

Cypress Semiconductor 

CY14B256Q1

CY14B256Q2

CY14B256Q3

Pin Definitions

Pin Name I/O Type

Description

CS

Input Chip select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low-power

standby mode.

SCK

Input

Serial clock. Runs

clock. Serial output

at speeds up to maximum of

is driven at the falling edge of

ftShCeKc.loScekr.ial

input

is

latched

at

the

rising

edge

of

this

SI

Input Serial input. Pin for input of all SPI instructions and data.

SO

Output Serial output. Pin for output of data through SPI.

WP

Input Write protect. Implements hardware write protection in SPI.

HOLD

Input HOLD pin. Suspends serial operation.

HSB

Input/output

Hardware STORE busy:

Output: Indicates busy status of nvSRAM when LOW. After each hardware and software STORE

operation HSB

internal pull-up

is driven HIGH

resistor keeps

ftohrisapsinhoHrtIGtimHe(e(txHtHeHrnDa)lwpiuthll-sutpanredsairsdtooructpountnheicgthiocnuorrpetniotnaanld).

then

a

weak

Input: Hardware STORE implemented by pulling this pin LOW externally.

VCAP

Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM

to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It must never

be connected to ground.

NC

No connect No connect: This pin is not connected to the die.

VSS Power supply Ground.

VCC Power supply Power supply (2.7 V to 3.6 V).

EXPOSED No connect The exposed pad on the bottom of 8-pin DFN package is not connected to the die. It is recommended

PAD

to connect the exposed pad to VSS. Thermal vias can be used to increase thermal conductivity.

Document Number: 001-53882 Rev. *J

Page 4 of 29

Share Link: