CY14B256Q3 查看數據表（PDF） - Cypress Semiconductor
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CY14B256Q3 Datasheet PDF : 26 Pages
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CY14B256Q1
CY14B256Q2
CY14B256Q3
Write Protect (WP) Pin
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This enables the user to install the device in a
system with the WP pin tied to ground, and still write to the Status
Register.
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to the Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
CY14B256Q2 does not have WP pin and therefore does not
provide hardware write protection.
Table 6 summarizes all the protection features of this device.
Table 6. Write Protection Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
X
X 0 Protected Protected Protected
0
X 1 Protected Writable Writable
1 LOW 1 Protected Writable Protected
1 HIGH 1 Protected Writable Writable
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Read Sequence (READ) instruction
The read operations on this device are performed by giving the
instruction on the SI pin and reading the output on SO pin. The
following sequence needs to be followed for a read operation:
After the CS line is pulled LOW to select a device, the read
opcode is transmitted through the SI line followed by two bytes
of address. The MSB bit (A15) of the address is a “don’t care”.
After the last address bit is transmitted on the SI pin, the data
(D7-D0) at the specific address is shifted out on the SO line on
the falling edge of SCK starting with D7. Any other data on SI line
after the last address bit is ignored.
CY14B256Q1/CY14B256Q2/CY14B256Q3 allows reads to be
performed in bursts through SPI which can be used to read
consecutive addresses without issuing a new READ instruction.
If only one byte is to be read, the CS line must be driven HIGH
after one byte of data comes out. However, the read sequence
may be continued by holding the CS line LOW and the address
is automatically incremented and data continues to shift out on
SO pin. When the last data memory address (0x7FFF) is
reached, the address rolls over to 0x0000 and the device
continues to read.
Write Sequence (WRITE) instruction
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is write disabled,
then the device must first be write enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by 2 bytes of address and the data (D7-D0) which is to
be written. The MSB bit (A15) of the address is a “don’t care”.
CY14B256Q1/CY14B256Q2/CY14B256Q3 enables writes to be
performed in bursts through SPI which can be used to write
consecutive addresses without issuing a new WRITE instruction.
If only one byte is to be written, the CS line must be driven HIGH
after the D0 (LSB of data) is transmitted. However, if more bytes
are to be written, CS line must be held LOW and address is
incremented automatically. The following bytes on the SI line are
treated as data bytes and written in the successive addresses.
When the last data memory address (0x7FFF) is reached, the
address rolls over to 0x0000 and the device continues to write.
The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Figure 9. Read Instruction Timing
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7
Op-Code
15-bit Address
0 0 0 0 0 0 1 1 X 14 13 12 11 10 9 8
MSB
HI-Z
32
10
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Data
LSB
Document Number: 001-53882 Rev. *E
Page 11 of 26
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