CY2213 查看數據表（PDF） - Cypress Semiconductor

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CY2213

High-Frequency Programmable PECL Clock Generator

Cypress Semiconductor 

CY2213

Figure 12 shows the definition of cycle-to-cycle duty cycle

error. Cycle-to-cycle duty cycle error is defined as the

difference between high-times of adjacent cycles over many

cycles (typically 12800 cycles at 400 MHz). Equal require-

ments apply to the low-times. tDC,ERR is defined as the clock

output cycle-to-cycle duty cycle error.

CLK

Figure 13 shows the definition of long-term jitter error.

Long-term jitter is defined as the accumulated timing error over

many cycles (typically 12800 cycles at 400 MHz). It applies to

both rising and falling edges. tJLT is defined as the long-term

jitter.

CLKB

CLK

tCYCLE

tJP = tCYCLE,max – tCYCLE, min. over many cycles

Figure 10. Period Jitter

CLKB

CLK

tCYCLE,i

tCYCLE, i+1

tJC = tCYLCE,i – tCYCLE,i+1 over many consecutive cycles

Figure 11. Cycle-to-cycle Jitter

Cycle i

Cycle i+1

CLKB

CLK

tPW+,i+1

tPW+,i

tCYCLE,i+1

tCYCLE, i+1

tDC,ERR = tPW+,i – tPW+,i+1 over many consecutive cycles

Figure 12. Cycle-to-cycle Duty Cycle Error

CLKB

tmin

tmax

tJLT = tmax – tmin over many cycles

Figure 13. Long-term Jitter

Document #: 38-07263 Rev. *E

Page 8 of 10

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