CY22394(2008) 查看數據表（PDF） - Cypress Semiconductor

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CY22394
(Rev.:2008)

Three-PLL Serial-Programmable Flash-Programmable Clock Generator

Cypress Semiconductor 

CY22393, CY22394, CY22395

Figure 3. Data Frame Architecture

SDAT Write

Multiple

Contiguous

Registers

1 Bit

1 Bit Slave

R/W = 0 ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

7-bit

Device

Address

8-bit

Register

Address

(XXH)

8-bit

Register

Data

(XXH)

8-bit

Register

Data

(XXH+1)

8-bit

Register

Data

(XXH+2)

Start Signal

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

8-bit

Register

Data

(FFH)

8-bit

Register

Data

(00H)

SDAT Read

1 Bit

1 Bit Slave

R/W = 1 ACK

1 Bit

Slave

ACK

Current

7-bit

Address

Device

Address

Read Start Signal

8-bit

Register

Data

1 Bit

Master

ACK

Stop Signal

SDAT Read

Multiple

Contiguous

Registers

1 Bit

1 Bit Slave

R/W = 0 ACK

1 Bit

Slave

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

7-bit

Device

Address

8-bit

Register

Address

(XXH)

7-bit

Device

Address

+R/W=1

8-bit

Register

Data

(XXH)

8-bit

Register

Data

(XXH+1)

Start Signal

Repeated

Start bit

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

8-bit

Register

Data

(FFH)

8-bit

Register

Data

(00H)

Figure 4. Data Valid and Data Transition Periods

Data Valid

Transition

to next Bit

SDAT

1 Bit

Slave

ACK

Stop Signal

1 Bit

Master

ACK

Stop Signal

tDH tSU

VIH

SCLK

VIL

CLKHIGH

CLKLOW

Serial Programming Interface Timing

Figure 5. Start and Stop Frame

START

Transition

to next Bit

STOP

SDAT

SCLK

Document #: 38-07186 Rev. *D

Page 11 of 19

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