CY22395(2008) 查看數據表（PDF） - Cypress Semiconductor

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CY22395
(Rev.:2008)

Three-PLL Serial-Programmable Flash-Programmable Clock Generator

Cypress Semiconductor 

CY22393, CY22394, CY22395

The Clock outputs have been designed to drive a single point

load with a total lumped load capacitance of 15 pF. While driving

multiple loads is possible with the proper termination it is

generally not recommended.

Power-Saving Features

The SHUTDOWN/OE input tri-states the outputs when pulled

LOW. If system shutdown is enabled, a LOW on this pin also

shuts off the PLLs, counters, reference oscillator, and all other

active components. The resulting current on the VDD pins is less

than 5 mA (typical). Relock the PLLs after leaving shutdown

mode.

The S2/SUSPEND input is configured to shut down a

customizable set of outputs and/or PLLs, when LOW. All PLLs

and any of the outputs are shut off in nearly any combination.

The only limitation is that if a PLL is shut off, all outputs derived

from it must also be shut off. Suspending a PLL shuts off all

associated logic, while suspending an output simply forces a

tri-state condition.

With the serial interface, each PLL and/or output is individually

disabled. This provides total control over the power savings.

Improving Jitter

Jitter Optimization Control is useful for mitigating problems

related to similar clocks switching at the same moment, causing

excess jitter. If one PLL is driving more than one output, the

negative phase of the PLL can be selected for one of the outputs

(CLKA–CLKD). This prevents the output edges from aligning,

allowing superior jitter performance.

Power Supply Sequencing

For parts with multiple VDD pins, there are no power supply

sequencing requirements. The part is not fully operational until

all VDD pins have been brought up to the voltages specified in

the Operating Conditions Table on page 13.

All grounds must be connected to the same ground plane.

CyClocksRT Software

CyClocksRT is our second generation software application that

allows users to configure this family of devices. The easy-to-use

interface offers complete control of the many features of this

family including, but not limited to, input frequency, PLL and

output frequencies, and different functional options. It checks

data sheet frequency range limitations and automatically applies

performance tuning. CyClocksRT also has a power estimation

feature that allows the user to see the power consumption of a

specific configuration. You can download a free copy of

CyberClocks that includes CyClocksRT for free on Cypress’s

web site at www.cypress.com.

CyClocksRT is used to generate P, Q, and divider values used

in serial programming. There are many internal frequency rules

that are not documented in this data sheet, but are required for

proper operation of the device. Check these rules by using the

latest version of CyClocksRT.

Junction Temperature Limitations

It is possible to program this family such that the maximum

Junction Temperature rating is exceeded. The package θJA is

115 °C/W. Use the CyClocksRT power estimation feature to

verify that the programmed configuration meets the Junction

Temperature and Package Power Dissipation maximum ratings.

Dynamic Updates

The output divider registers are not synchronized with the output

clocks. Changing the divider value of an active output is likely

cause a glitch on that output.

PLL P and Q data is spread between three bytes. Each byte

becomes active on the acknowledge for that byte, so changing

P and Q data for an active PLL is likely cause the PLL to try to

lock on an out-of-bounds condition. For this reason, turn off the

PLL being programmed during the update. Do this by setting the

PLL*_En bit LOW.

PLL1, CLKA, and CLKB each have multiple registers supplying

data. To program these resources safely, always program an

inactive register, and then transition to that register. This allows

these resources to stay active during programming.

The serial interface is active even with the SHUTDOWN/OE pin

LOW as the serial interface logic uses static components and is

completely self timed. The part does not meet the IDDS current

limit with transitioning inputs.

Memory Bitmap Definitions

Clk{A–D}_Div[6:0]

Each of the four main output clocks (CLKA–CLKD) features a

7-bit linear output divider. Any divider setting between 1 and 127

may be used by programming the value of the desired divider

into this register. Odd divide values are automatically duty cycle

corrected. Setting a divide value of zero powers down the divider

and forces the output to a tri-state condition.

CLKA and CLKB have two divider registers, selected by the

DivSel bit (which in turn is selected by S2, S1, and S0). This

allows the output divider value to change dynamically. For the

CY22394 device, ClkD_Div = 000001.

ClkE_Div[1:0]

CLKE has a simpler divider (see Table 1). For the CY22394, set

ClkE_Div = 01.

Table 1. ClkE Divider

ClkE_Div[1:0]

00

01

10

11

ClkE Output

Off

PLL1 0° Phase/4

PLL1 0° Phase/2

PLL1 0° Phase/3

Document #: 38-07186 Rev. *D

Page 6 of 19

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