CY22394(2008) 查看數據表（PDF） - Cypress Semiconductor
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CY22394
(Rev.:2008)
(Rev.:2008)
Cypress Semiconductor
CY22394 Datasheet PDF : 19 Pages
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CY22393, CY22394, CY22395
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These must
always be set according to Table 5. The parameters are the
Crystal Frequency, Internal Crystal Parasitic Resistance
(available from the manufacturer), and the OscCap setting
during crystal start up, which occurs when power is applied, or
after shutdown is released. If in doubt, use the next higher
setting.
Table 5. Crystal Oscillator Gain Settings
OscCap
00H–20H
Crystal Freq\ R 30Ω 60Ω
8–15 MHz 00 01
15–20 MHz 01 10
20–25 MHz 01 10
25–30 MHz 10 10
20H–30H
30Ω 60Ω
01 10
01 10
10 10
10 11
30H–40H
30Ω 60Ω
01 10
10 10
10 11
11 NA
For external reference, the use Table 6.
Table 6. Osc Drv for External Reference
External Freq (MHz) 1–25 25–50 50–90
OscDrv[1:0]
00
01
10
90–166
11
Reserved
These bits must be programmed LOW for proper operation of the
device.
Serial Programming Bitmaps — Summary Tables
Addr
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
DivSel
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
b7
b6
ClkA_FS[0]
ClkA_FS[0]
ClkB_FS[0]
ClkB_FS[0]
ClkC_FS[0]
ClkD_FS[0]
ClkD_FS[2:1]
Clk{C,X}_ACAdj[1:0]
ClkX_DCAdj[1]
Reserved PLL2_En
Reserved PLL3_En
b5
b4
b3
b2
ClkA_Div[6:0]
ClkA_Div[6:0]
ClkB_Div[6:0]
ClkB_Div[6:0]
ClkC_Div[6:0]
ClkD_Div[6:0]
ClkC_FS[2:1]
ClkB_FS[2:1]
Clk{A,B,D,E}_ACAdj[1:0] PdnEn Xbuf_OE
Clk{D,E}_DCAdj[1]
ClkC_DCAdj[1]
PLL2_Q[7:0]
PLL2_P[7:0]
PLL2_LF[2:0]
PLL2_PO
PLL3_Q[7:0]
PLL3_P[7:0]
PLL3_LF[2:0]
PLL3_PO
Osc_Cap[5:0]
b1
b0
ClkA_FS[2:1]
ClkE_Div[1:0]
Clk{A,B}_DCAdj[1]
PLL2_P[9:8]
PLL3_P[9:8]
Osc_Drv[1:0]
Addr S2 (1,0)
40H 000
41H
42H
43H 001
44H
45H
46H 010
47H
48H
b7
DivSel
DivSel
DivSel
b6
PLL1_En
PLL1_En
PLL1_En
b5
b4
b3
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
b2
PLL1_PO
PLL1_PO
PLL1_PO
b1
b0
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
Document #: 38-07186 Rev. *D
Page 8 of 19
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