CY7B992-7LMB(2001) 查看數據表（PDF） - Cypress Semiconductor

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CY7B992-7LMB
(Rev.:2001)

Programmable Skew Clock Buffer

Cypress Semiconductor 

CY7B991

CY7B992

Operational Mode Descriptions

REF

LOAD

SYSTEM

CLOCK

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

LENGTH L1 = L2 = L3 = L4

L1

Z0

LOAD

L2

Z0

L3

Z0

LOAD

L4

LOAD

Z0

7B991–9

Figure 2. Zero-Skew and/or Zero-Delay Clock Driver

Figure 2 shows the PSCB configured as a zero-skew clock

buffer. In this mode the 7B991/992 can be used as the basis

for a low-skew clock distribution tree. When all of the function

select inputs (xF0, xF1) are left open, the outputs are aligned

and may each drive a terminated transmission line to an inde-

pendent load. The FB input can be tied to any output in this

configuration and the operating frequency range is selected

with the FS pin. The low-skew specification, coupled with the

ability to drive terminated transmission lines (with impedances

as low as 50 ohms), allows efficient printed circuit board de-

sign.

REF

LOAD

SYS–

TEM

CLOCK

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

LENGTH L1 = L2

L3 < L2 by 6 inches

L4 > L2 by 6 inches

L1

Z0

LOAD

L2

Z0

L3

Z0

LOAD

L4

LOAD

Z0

7B991–10

Figure 3. Programmable-Skew Clock Driver

Figure 3 shows a configuration to equalize skew between met-

al traces of different lengths. In addition to low skew between

outputs, the PSCB can be programmed to stagger the timing

of its outputs. The four groups of output pairs can each be

programmed to different output timing. Skew timing can be

adjusted over a wide range in small increments with the appro-

priate strapping of the function select pins. In this configuration

the 4Q0 output is fed back to FB and configured for zero skew.

The other three pairs of outputs are programmed to yield dif-

ferent skews relative to the feedback. By advancing the clock

signal on the longer traces or retarding the clock signal on

shorter traces, all loads can receive the clock pulse at the

same time.

In this illustration the FB input is connected to an output with

0-ns skew (xF1, xF0 = MID) selected. The internal PLL syn-

chronizes the FB and REF inputs and aligns their rising edges

to insure that all outputs have precise phase alignment.

Clock skews can be advanced by ±6 time units (tU) when using

an output selected for zero skew as the feedback. A wider range of

delays is possible if the output connected to FB is also skewed.

Since “Zero Skew”, +tU, and –tU are defined relative to output

groups, and since the PLL aligns the rising edges of REF and FB,

it is possible to create wider output skews by proper selection of the

xFn inputs. For example a +10 tU between REF and 3Qx can be

achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,

Document #: 38-07138 Rev. **

Page 10 of 15

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