CY7B992-7LMB(2001) 查看數據表（PDF） - Cypress Semiconductor
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CY7B992-7LMB Datasheet PDF : 15 Pages
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CY7B991
CY7B992
Switching Characteristics Over the Operating Range[2, 13] (continued)
Parameter
fNOM
tRPWH
tRPWL
tU
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
Description
Operating Clock
Frequency in MHz
FS = LOW[1, 2]
FS = MID[1, 2]
FS = HIGH[1, 2 , 3]
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17]
Zero Output Skew (All Outputs)[16, 18]
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 20]
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 20]
CY7B991–5
CY7B992–5
Min. Typ. Max. Min. Typ. Max.
15
30
15
30
25
50
25
50
40
80
40
80[15]
5.0
5.0
5.0
5.0
See Table 1
0.1 0.25
0.1 0.25
0.25 0.5
0.6
0.7
0.25 0.5
0.6
0.7
0.5
1.0
0.6
1.5
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 20]
0.5
0.7
0.5
0.7
tSKEW4
tDEV
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 20]
Device-to-Device Skew[14, 21]
0.5
1.0
1.25
0.6
1.7
1.25
Propagation Delay, REF Rise to FB Rise
–0.5 0.0 +0.5 –0.5 0.0 +0.5
Output Duty Cycle Variation[22]
–1.0 0.0 +1.0 –1.2 0.0 +1.2
Output HIGH Time Deviation from 50%[23, 24]
2.5
4.0
Output LOW Time Deviation from 50%[23, 24]
3
4.0
Output Rise Time[23, 25]
0.15 1.0
1.5
0.5
2.0
3.5
Output Fall Time[23, 25]
0.15 1.0
1.5
0.5
2.0
3.5
PLL Lock Time[26]
0.5
0.5
Cycle-to-Cycle Output RMS[14]
25
25
Jitter
Peak-to-Peak[14]
200
200
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Document #: 38-07138 Rev. **
Page 7 of 15
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