CY7B9940V 查看數據表（PDF） - Cypress Semiconductor

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CY7B9940V

High Speed Multifrequency PLL Clock Buffer

Cypress Semiconductor 

RoboClockII™ Junior,

CY7B9930V, CY7B9940V

The HOLD OFF state is designed as a power saving feature. An

output bank is disabled to the HOLD OFF state in a maximum of

six output clock cycles from the time when the disable input

(DIS[1:2]) is HIGH. When disabled to the HOLD OFF state,

outputs are driven to a logic LOW state on its falling edge. This

ensures the output clocks are stopped without glitch. When a

bank of outputs is disabled to HI-Z state, the respective bank of

outputs go HI-Z immediately.

Table 3. DIS[1:2] Pin Functionality

OUTPUT_MODE

HIGH/LOW

HIGH

LOW

MID

DIS[1:2]/FBDIS

LOW

HIGH

HIGH

X

Output Mode

ENABLED

HI-Z

HOLD-OFF

FACTORY TEST

Lock Detect Output Description

The LOCK detect output indicates the lock condition of the

integrated PLL. Lock detection is accomplished by comparing

the phase difference between the reference and feedback

inputs. Phase error is declared when the phase difference

between the two inputs is greater than the specified device

propagation delay limit (tPD).

When in the locked state, after four or more consecutive

feedback clock cycles with phase errors, the LOCK output is

forced LOW to indicate out-of-lock state.

When in the out-of-lock state, 32 consecutive phase errorless

feedback clock cycles are required to allow the LOCK output to

indicate lock condition (LOCK = HIGH).

If the feedback clock is removed after LOCK has gone HIGH, a

Watchdog circuit is implemented to indicate the out-of-lock

condition after a timeout period by deasserting LOCK LOW. This

timeout period is based upon a divided down reference clock.

This assumes that there is activity on the selected REF input. If

there is no activity on the selected REF input then the LOCK

detect pin may not accurately reflect the state of the internal PLL.

Factory Test Mode Description

The device enters factory test mode when the OUTPUT_MODE

is driven to MID. In factory test mode, the device operates with

its internal PLL disconnected; the input level supplied to the

reference input is used in place of the PLL output. In TEST mode

the selected FB input must be tied LOW. All functions of the

device remain operational in factory test mode except the

internal PLL and output bank disables. The OUTPUT_MODE

input is designed as a static input. Dynamically toggling this input

from LOW to HIGH may temporarily cause the device to go into

factory test mode (when passing through the MID state).

Factory Test Reset

When in factory test mode (OUTPUT_MODE = MID), the device

is reset to a deterministic state by driving the DIS2 input HIGH.

When the DIS2 input is driven HIGH in factory test mode, all

clock outputs go to HI-Z; after the selected reference clock pin

has five positive transitions, all the internal finite state machines

(FSM) are set to a deterministic state. The deterministic state of

the state machines depends on the configurations of the divide

selects and frequency select input. All clock outputs stay in high

impedance mode and all FSMs stay in the deterministic state

until DIS2 is deasserted. When DIS2 is deasserted (with

OUTPUT_MODE still at MID), the device reenters factory test

mode.

Document Number: 38-07271 Rev. *C

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