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CY7B9940V 查看數據表(PDF) - Cypress Semiconductor

零件编号
产品描述 (功能)
生产厂家
CY7B9940V
Cypress
Cypress Semiconductor Cypress
CY7B9940V Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Absolute Maximum Conditions
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ...........................................−40°C to +125°C
Ambient Temperature with power applied ........−40°C to +125°C
Supply voltage to ground potential ........................−0.5V to +4.6V
DC input voltage ............................................... −0.3V to VCC+0.5V
Output current into outputs (LOW) ...................................40 mA
Static discharge voltage................................................. >2000V
MIL-STD-883, Method 3015)
Latch up current......................................................... >±200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ±10%
3.3V ±10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
LVTTL HIGH voltage QFA[0:1], [1:2]Q[A:B][0:1] VCC = Min., IOH = –30 mA 2.4
V
LOCK
IOH = –2 mA, VCC = Min.
2.4
V
VOL
LVTTL LOW voltage QFA[0:1], [1:2]Q[A:B][0:1]
VCC = Min., IOL= 30 mA
0.5
V
LOCK
IOL= 2 mA, VCC = Min.
0.5
V
IOZ
High impedance state leakage current
–100
100
μA
LVTTL Compatible Input Pins (FBKA, REFA±, REFB±, REFSEL, DIS[1:2])
VIH
LVTTL Input HIGH FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
VIL
LVTTL Input LOW FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
Min. < VCC < Max.
Min. < VCC < Max.
2.0
VCC+0.3
V
2.0
VCC+0.3
V
–0.3
0.8
V
–0.3
0.8
V
II
LVTTL VIN >VCC
FBKA+, REF[A:B]±
VCC = GND, VIN = 3.63V
100
μA
IlH
LVTTL Input HIGH FBKA+, REF[A:B]±
Current
REFSEL, DIS[1:2]
VCC = Max., VIN = VCC
VIN = VCC
500
μA
500
μA
IlL
LVTTL Input LOW FBKA+, REF[A:B]±
VCC = Max., VIN = GND
–500
μA
Current
REFSEL, DIS[1:2]
–500
μA
3-Level Input Pins (FBDS[0:1], FS, Output_Mode)
VIHH
VIMM
VILL
Three level input HIGH[4]
Three level input MID[4]
Three level input LOW[4]
IIHH
Three level input Three level input pins
HIGH current
Min. < VCC < Max.
0.87*VCC
V
Min. < VCC < Max.
0.47*VCC 0.53*VCC
V
Min. < VCC < Max.
0.13*VCC
V
VIN = VCC
200
μA
IIMM
Three level input MID Three level input pins
current
VIN = VCC/2
–50
50
μA
IILL
Three level input Three level input pins
LOW current
VIN = GND
–200
μA
LVDIFF Input Pins (REF[A:B]±)
VDIFF
Input differential voltage
400
VCC
mV
VIHHP
Highest input HIGH voltage
1.0
VCC
V
VILLP
Lowest input LOW voltage
GND VCC – 0.4
V
VCOM
Common mode range (crossing voltage)
0.8
VCC
V
Note
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all data sheet limits are achieved.
Document Number: 38-07271 Rev. *C
Page 5 of 11
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