CY7C008V-20 查看數據表（PDF） - Cypress Semiconductor
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CY7C008V-20 Datasheet PDF : 18 Pages
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CY7C008V/009V
CY7C018V/019V
Switching Characteristics Over the Operating Range[10] (continued)
Parameter
Description
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[17]
BUSY HIGH to Data Valid
INTERRUPT TIMING[16]
tINS
INT Set Time
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
tSAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CY7C008V/009V
CY7C018V/019V
-15
-20
-25
Min. Max. Min. Max. Min. Max. Unit
13
15
17
ns
15
20
25
ns
15
20
20
ns
15
20
20
ns
10
10
12
ns
5
5
5
ns
5
5
5
ns
15
20
25
ns
Data Retention Mode
The CY7C008V/009V and CY7018V/019V are designed with
battery backup in mind. Data retention voltage and supply
current are guaranteed over temperature. The following rules
ensure data retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
Timing
VCC
CE
Data Retention Mode
3.0V
VCC > 2.0V
3.0V
tRC
VCC to VCC – 0.2V
VIH
Parameter
Test Conditions[18] Max. Unit
ICCDR1
@ VCCDR = 2V
50
µA
Notes:
17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
18. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06044 Rev. *C
Page 7 of 18
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