CY7C026AV-20AXC(2005) 查看數據表（PDF） - Cypress Semiconductor

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CY7C026AV-20AXC
(Rev.:2005)

3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No. 1 (Either Port Address Access)[28, 29, 30]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (Either Port CE/OE Access)[28, 31, 32]

CE and

LB or UB

OE

DATA OUT

ICC

CURRENT

ISB

tACE

tDOE

tLZOE

tLZCE

tPU

Read Cycle No. 3 (Either Port)[28, 30, 31, 32]

tRC

ADDRESS

tAA

UB or LB

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

CY7C024AV/025AV/026AV

CY7C0241AV/0251AV/036AV

DATA VALID

tOHA

tHZCE

tHZOE

DATA VALID

tPD

tOHA

tHZCE

tHZCE

Notes:

28. R/W is HIGH for read cycles.

29. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

30. OE = VIL.

31. Address valid prior to or coincident with CE transition LOW.

32. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

Document #: 38-06052 Rev. *H

Page 11 of 19

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