CY7C026A(2000) 查看數據表（PDF） - Cypress Semiconductor

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CY7C026A
(Rev.:2000)

16K x 16/18 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No.1 (Either Port Address Access)[19, 20, 21]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No.2 (Either Port CE/OE Access)[19, 22, 23]

CE and

LB or UB

OE

DATA OUT

ICC

CURRENT

ISB

tACE

tDOE

tLZOE

tLZCE

tPU

Read Cycle No. 3 (Either Port)[19, 21, 22, 23]

tRC

ADDRESS

tAA

UB or LB

CE

DATA OUT

tLZCE

tABE

tACE

tLZCE

CY7C026A

CY7C036A

DATA VALID

tOHA

tHZCE

tHZOE

DATA VALID

tPD

tOHA

tHZCE

tHZCE

Notes:

19. R/W is HIGH for read cycles.

20. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

21. OE = VIL.

22. Address valid prior to or coincident with CE transition LOW.

23. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

9

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