CY7C1020D-10VXI 查看數據表（PDF） - Cypress Semiconductor
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CY7C1020D-10VXI Datasheet PDF : 15 Pages
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CY7C1020D
Switching Characteristics (Over the Operating Range) [6]
Parameter
Read Cycle
tpower [7]
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU [10]
tPD [10]
tDBE
tLZBE
tHZBE
Write Cycle [11, 12]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Description
VCC(typical) to the first access
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low Z [9]
OE HIGH to High Z [8, 9]
CE LOW to Low Z [9]
CE HIGH to High Z [8, 9]
CE LOW to power-up
CE HIGH to power-down
Byte enable to data valid
Byte enable to Low Z
Byte disable to High Z
Write cycle time
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
Data set-up to write end
Data hold from write end
WE HIGH to Low Z [9]
WE LOW to High Z [8, 9]
Byte enable to end of write
–10 (Industrial)
Unit
Min
Max
100
s
10
ns
10
ns
3
ns
10
ns
5
ns
0
ns
5
ns
3
ns
5
ns
0
ns
10
ns
5
ns
0
ns
5
ns
10
ns
7
ns
7
ns
0
ns
0
ns
7
ns
6
ns
0
ns
3
ns
5
ns
7
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8.
otHuZtpOuEt,stHeZnBteEr,atHhZiCgEh,imanpdetdHaZnWcEe
are specified
state.
with
a
load
capacitance
of
5
pF
as
in
part
(c)
of
“AC
Test
Loads
and
Waveforms
[5]”
on
page
5.
Transition
is
measured
when
the
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write and
the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05463 Rev. *G
Page 6 of 15
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