CY7C1031-8(1995) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1031-8 Datasheet PDF : 14 Pages
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PRELIMINARY
CY7C1031
CY7C1032
Switching Characteristics Over the Operating Range[9]
7C1031–7 7C1031–8 7C1031–10 7C1031–12
7C1032–7 7C1032–8 7C1032–10 7C1032–12
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
Clock Cycle Time
13.3
15
15
20
ns
tCH
Clock HIGH
5
5
6
8
ns
tCL
Clock LOW
5
5
6
8
ns
tAS
Address Set-Up Before CLK Rise
2.5
2.5
2.5
2.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCDV
Data Output Valid After CLK Rise
7
8.5
10
12 ns
tDOH
Data Output Hold After CLK Rise
2
3
3
3
ns
tADS
ADSP, ADSC Set-Up Before CLK Rise
2.5
2.5
2.5
2.5
ns
tADSH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tWES
WH, WL Set-Up Before CLK Rise
2.5
2.5
2.5
2.5
ns
tWEH
WH, WL Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
2.5
2.5
2.5
2.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
2.5
2.5
2.5
2.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCSS
Chip Select Set-Up
2.5
2.5
2.5
2.5
ns
tCSH
tCSOZ
tEOZ
Chip Select Hold After CLK Rise
Chip Select Sampled to Output High Z[10]
OE HIGH to Output High Z[10]
0.5
0.5
0.5
0.5
ns
2
6
2
6
2
6
2
7 ns
2
6
2
6
2
6
2
7 ns
tEOV
OE LOW to Output Valid
5
tWEOZ
WH or WL Sampled LOW to Output High Z[10, 11]
5
tWEOV
WH or WL Sampled HIGH to Output Valid[11]
7
5
5
5
6
8.5
10
6 ns
7 ns
12 ns
Shaded areas contain advanced information
Notes:
9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) os AC test loads.
10. tCSOZ, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
11. At any given voltage and temperature, tWEOZ min. is less than tWEOV min.
7
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