80960CF-40(2002) 查看數據表（PDF） - Intel

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80960CF-40
(Rev.:2002)

32-Bit High-Performance Superscalar Embedded Microprocessor

Intel 

80960-40, -33, -25

2.2

Pipelined, Burst Bus

A 32-bit high performance bus controller interfaces the 80960CF to external memory and

peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at

40 MHz). Internally programmable wait states and 16 separately configurable memory regions

allow the processor to interface with a variety of memory subsystems with a minimum of system

complexity and a maximum of performance. The Bus Control Unit’s main features include:

• Demultiplexed, burst bus to exploit most efficient DRAM access modes

• Address pipelining to reduce memory cost while maintaining performance

• 32-, 16- and 8-bit modes for I/O interfacing ease

• Full internal wait state generation to reduce system cost

• Little and Big Endian support to ease application development

• Unaligned access support for code portability

• Three-deep request queue to decouple the bus from the core

2.3

Instruction Set Summary

Table 1 summarizes the 80960CF instruction set by logical groupings. For a complete description

of the instruction set, see the i960® CA/CF Microprocessor User’s Manual (order number 270710).

2.4

Flexible DMA Controller

A four-channel DMA controller provides high speed DMA control for data transfers involving

peripherals and memory. The DMA provides advanced features such as data chaining, byte

assembly and disassembly and a high performance fly-by mode capable of transfer speeds of up to

71 Mbytes per second at 40 MHz. The DMA controller features a performance and flexibility

which is only possible by integrating the DMA controller and the 80960CF core.

2.5

Priority Interrupt Controller

A programmable-priority interrupt controller manages up to 248 external sources through the 8-bit

external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA

controller and a single non-maskable interrupt input. The 8-bit interrupt port may also be

configured to provide individual interrupt sources that are level or edge triggered.

80960CF interrupts are prioritized and signaled within 225 ns of the request. When the interrupt is

of higher priority than the processor priority, the context switch to the interrupt routine typically

completes in another 400 ns. The interrupt unit provides the mechanism for the low latency and

high throughput interrupt service which is essential for embedded applications.

Table 1 presents the 80960CF Instruction Set.

Datasheet

9

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