CY7C1218F 查看數據表（PDF） - Cypress Semiconductor
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CY7C1218F Datasheet PDF : 16 Pages
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CY7C1218F
Switching Characteristics Over the Operating Range[11, 12]
166 MHz
133 MHz
Parameter
Description
tPOWER
VDD(Typical) to the First Access[13]
Clock
Min. Max Min. Max
Unit
1
1
ms
tCYC
Clock Cycle Time
tCH
Clock HIGH
tCL
Clock LOW
Output Times
6.0
7.5
ns
2.5
3.0
ns
2.5
3.0
ns
tCO
Data Output Valid after CLK Rise
tDOH
tCLZ
tCHZ
Data Output Hold after CLK Rise
Clock to Low-Z[14, 15, 16]
Clock to High-Z[14, 15, 16]
tOEV
tOELZ
tOEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z[14, 15, 16]
OE HIGH to Output High-Z[14, 15, 16]
Set-up Times
3.5
4.0
ns
2.0
2.0
ns
0
0
ns
3.5
4.0
ns
3.5
4.5
ns
0
0
ns
3.5
4.0
ns
tAS
Address Set-up before CLK Rise
tADS
ADSC, ADSP Set-up before CLK Rise
tADVS
ADV Set-up before CLK Rise
tWES
tDS
GW, BWE, BW[A:D] Set-up before CLK Rise
Data Input Set-up before CLK Rise
tCES
Chip Enable Set-Up before CLK Rise
Hold Times
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.5
0.5
ns
tADH
ADSP , ADSC Hold aAfter CLK Rise
0.5
0.5
ns
tADVH
ADV Hold after CLK Rise
0.5
0.5
ns
tWEH
tDH
GW,BWE, BW[A:D] Hold after CLK Rise
Data Input Hold after CLK Rise
0.5
0.5
ns
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
0.5
ns
Notes:
11. Timing reference level is 1.5V when VDDQ = 3.3V.
12. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
can be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document #: 38-05422 Rev. **
Page 10 of 16
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