CY7C1302DV25(2004) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1302DV25
(Rev.:2004)
(Rev.:2004)
Cypress Semiconductor
CY7C1302DV25 Datasheet PDF : 18 Pages
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PREMILINARY
CY7C1302DV25
Thermal Resistance[16]
Parameter
Description
ΘJA Thermal Resistance (Junction to Ambient)
ΘJC Thermal Resistance (Junction to Case)
Test Conditions
165 FBGA Package Unit
Test conditions follow standard test
16.7
°C/W
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
2.5
°C/W
Capacitance[16]
CIN
CCLK
CO
Parameter
Description
Input Capacitance
Clock Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 2.5V.
VDDQ = 1.5V
Max. Unit
5
pF
6
pF
7
pF
AC Test Loads and Waveforms
VREF
OUTPUT
Device
Under
Test
ZQ
(a)
VDDQ/2
Z0 = 50Ω
RQ =
250Ω
VREF
RL = 50Ω
VREF = 0.75V
OUTPUT
Device
Under
Test ZQ
INCLUDING
JIG AND
SCOPE
VDDQ/2
VDDQ/2
R = 50Ω
RQ =
250Ω
(b)
5 pF 0.25V
[17]
ALL INPUT PULSES
1.25V
0.75V
Switching Characteristics Over the Operating Range [17]
Cypress
Parameter
tPower[18]
Cycle Time
Consortium
Parameter
Description
VCC (typical) to the First Access Read or Write
167 MHz 133 MHz 100 MHz
Min. Max. Min. Max. Min. Max. Unit
10
10
10
µs
tCYC
tKH
tKL
tKHKH
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle Time
6.0
7.5
10.0
ns
Input Clock (K/K and C/C) HIGH
2.4
3.2
3.5
ns
Input Clock (K/K and C/C) LOW
2.4
3.2
3.5
ns
K/K Clock Rise to K/K Clock Rise and C/C to C/C 2.7 3.3 3.4 4.1 4.4 5.4 ns
Rise (rising edge to rising edge)
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0 2.0 0.0 2.5 0.0 3.0 ns
rising edge)
Set-up Times
tSA
tSA
Address Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
tSC
tSC
Control Set-up to Clock (K and K) Rise (RPS, 0.7
0.8
1.0
ns
WPS, BWS0, BWS1)
tSD
tSD
D[17:0] Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
Notes:
16. Tested initially and after any design or process change that may affect these parameters.
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
18. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read
or write operation can be initiated.
Document #: 38-05625 Rev. **
Page 7 of 18
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