CY7C1302DV25(2004) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1302DV25
(Rev.:2004)

9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

Cypress Semiconductor 

Switching Waveforms[21, 22, 23]

PREMILINARY

READ

1

WRITE

2

READ

3

WRITE

4

READ

5

WRITE

NOP

6

7

K

tKH

tKL

tCYC

tKHKH

K

CY7C1302DV25

WRITE

8

NOP

9

10

RPS

tSC

tHC

WPS

A A0

A1

A2

A3

A4

A5

A6

D D10

tSA tHA

D11

tSA tHA

D30

D31

D50

tSD

tHD

D51

D60

tSD

D61

tHD

Q

Q00

Q01

Q20

Q21

Q40

tKHCH

tKHCH

tCLZ

tDOH

tDOH

tCO

tCO

C

tKH

tKL

tKHKH

tCYC

C

Q41

tCHZ

DON’T CARE

UNDEFINED

Notes:

21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

22. Outputs are disabled (High-Z) one clock cycle after a NOP.

23. In this example, if address A2=A1 then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.

Document #: 38-05625 Rev. **

Page 9 of 18

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