CY7C1334H-133AXC 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY7C1334H-133AXC

2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

Switching Waveforms (continued)

NOP, STALL, and Deselect Cycles[18, 19, 21]

1

2

3

4

5

CLK

CEN

CE

ADV/LD

WE

BW[A:D]

ADDRESS A1 A2

A3

A4

Data

D(A1) Q(A2)

In-Out (DQ)

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

6

7

Q(A3)

STALL

NOP

CY7C1334H

8

9

10

A5

D(A4)

tCHZ

Q(A5)

READ

Q(A5)

DESELECT CONTINUE

DESELECT

ZZ Mode Timing[22, 23]

CLK

ZZ

I SUPPLY

ALL INPUTS

(except ZZ)

DON’T CARE

UNDEFINED

t ZZ

t ZZI

I DDZZ

t ZZREC

t RZZI

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

22. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

23. I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05678 Rev. *B

Page 11 of 13

[+] Feedback

Share Link: