CY7C1334H-133AXC 查看數據表（PDF） - Cypress Semiconductor
零件编号
产品描述 (功能)
生产厂家
CY7C1334H-133AXC Datasheet PDF : 13 Pages
| |||
CY7C1334H
Maximum Rating
(Above which the useful life may be impaired. For user guide-
lines not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND .......−0.5V to +VDD
DC Voltage Applied to Outputs
in Tri-State ................................................−0.5V to VDDQ + 0.5V
DC Input Voltage ....................................... −0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature (TA)
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
3.3V - 5%/+10% 2.5V - 5% to
VDD
Electrical Characteristics Over the Operating Range[9, 10]
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
Power Supply Voltage
I/O Supply Voltage
for 3.3V I/O
for 2.5V I/O
3.135
3.135
2.375
VOH
Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA
2.4
for 2.5V I/O, IOH = –1.0 mA
2.0
VOL
Output LOW Voltage
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
VIH
Input HIGH Voltage[9] for 3.3V I/O
2.0
for 2.5V I/O
1.7
VIL
Input LOW Voltage[9] for 3.3V I/O
–0.3
for 2.5V I/O
–0.3
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
–5
except ZZ and MODE
Input Current of MODE Input = VSS
−30
Input = VDD
Input Current of ZZ
Input = VSS
−5
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
−5
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
6-ns cycle, 166 MHz
Current
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
ISB1
Automatic CE
Power-Down
VDD = Max, Device
Deselected,
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
ISB2
Automatic CE
VDD = Max, Device
All speeds
Power-Down
Deselected, VIN ≤ 0.3V or
Current—CMOS Inputs VIN > VDDQ – 0.3V, f = 0
ISB3
Automatic CE
VDD = Max, Device
6-ns cycle, 166 MHz
Power-Down
Deselected, or VIN ≤ 0.3V or 7.5-ns cycle, 133 MHz
Current—CMOS Inputs VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
ISB4
Automatic CE
Power-Down
VDD = Max, Device
Deselected,
All Speeds
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL, f = 0
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Max. Unit
3.6
V
VDD
V
2.625
V
V
0.4
V
0.4
VDD + 0.3V V
VDD + 0.3V
0.8
V
0.7
5
µA
µA
5
µA
µA
30
µA
5
µA
240
mA
225
mA
100
mA
90
mA
40
mA
85
mA
75
mA
45
mA
Document #: 38-05678 Rev. *B
Page 7 of 13
[+] Feedback
Share Link: 