CY7C1334H-133AXC 查看數據表（PDF） - Cypress Semiconductor
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CY7C1334H-133AXC Datasheet PDF : 13 Pages
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CY7C1334H
Switching Characteristics Over the Operating Range [12, 13]
166 MHz
133 MHz
Parameter
tPOWER
Clock
Description
VDD (typical) to the First Access[14]
Min. Max. Min. Max. Unit
1
1
ms
tCYC
tCH
tCL
Output Times
Clock Cycle Time
Clock HIGH
Clock LOW
6.0
7.5
ns
2.5
3.0
ns
2.5
3.0
ns
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[15, 16, 17]
Clock to High-Z[15, 16, 17]
OE LOW to Output Valid
OE LOW to Output Low-Z[15, 16, 17]
OE HIGH to Output High-Z[15, 16, 17]
3.5
4.0
ns
1.5
1.5
ns
0
0
ns
3.5
4.0
ns
3.5
4.0
ns
0
0
ns
3.5
4.0
ns
tAS
tALS
tWES
tCENS
tDS
tCES
Hold Times
Address Set-up before CLK Rise
ADV/LD Set-up before CLK Rise
GW, BW[A:D] Set-up before CLK Rise
CEN Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
ns
tWEH
GW, BW[A:D] Hold after CLK Rise
0.5
0.5
ns
tCENH
CEN Hold after CLK Rise
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
0.5
ns
Notes:
12. Test conditions shown in (a), (b) and (c) of AC Test Loads.
13. Timing reference level is 1.5V when VDDQ = 3.3V and 1.25V when VDDQ = 2.5V.
14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
15. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Tri-State prior to Low-Z under the same system conditions
17. This parameter is sampled and not 100% tested.
Document #: 38-05678 Rev. *B
Page 9 of 13
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