CY7C1326F 查看數據表（PDF） - Cypress Semiconductor
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CY7C1326F Datasheet PDF : 15 Pages
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CY7C1326F
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ..................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
VDD
3.3V
–5%/+10%
VDDQ
3.3V –5%
to VDD
Electrical Characteristics Over the Operating Range[8, 9]
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[8]
Input LOW Voltage[8]
Input Load Current
except ZZ and MODE
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 3.3V
VDDQ = 3.3V
GND ≤ VI ≤ VDDQ
3.135
3.135
2.4
2.0
–0.3
–5
Input Current of MODE Input = VSS
–30
Input = VDD
Input Current of ZZ
Input = VSS
–5
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA, 7.5-ns cycle, 133 MHz
Current
f = fMAX = 1/tCYC
10-ns cycle, 100 MHz
ISB1
Automatic CS
VDD = Max, Device
7.5-ns cycle, 133 MHz
Power-down
Current—TTL Inputs
Deselected, VIN ≥ VIH or
VIN ≤ VIL, f = fMAX = 1/tCYC
10-ns cycle, 100 MHz
ISB2
Automatic CS
VDD = Max, Device
All speeds
Power-down
Deselected, VIN ≤ 0.3V or
Current—CMOS Inputs VIN > VDDQ – 0.3V, f = 0
ISB3
Automatic CS
VDD = Max, Device
7.5-ns cycle, 133 MHz
Power-down
Deselected, or VIN ≤ 0.3V 10-ns cycle, 100 MHz
Current—CMOS Inputs or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
ISB4
Automatic CS
VDD = Max, Device
All speeds
Power-down
Deselected, VIN ≥ VIH or
Current—TTL Inputs VIN ≤ VIL, f = 0
Notes:
8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Max. Unit
3.6
V
VDD
V
V
0.4
V
VDD + 0.3V V
0.8
V
5
µA
µA
5
µA
µA
30
µA
5
µA
225 mA
205 mA
90
mA
80
mA
40
mA
75
mA
65
mA
45
mA
Document #: 38-05424 Rev. **
Page 7 of 15
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