CY7C1326F 查看數據表（PDF） - Cypress Semiconductor
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CY7C1326F Datasheet PDF : 15 Pages
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CY7C1326F
Switching Characteristics Over the Operating Range[11, 12]
133 MHz
100 MHz
Parameter
tPOWER
Clock
Description
VDD(Typical) to the First Access[13]
Min.
Max
Min.
Max
Unit
1
1
1
ms
tCYC
tCH
tCL
Output Times
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
10
ns
3.0
3.5
ns
3.0
3.5
ns
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[14, 15, 16]
Clock to High-Z[14, 15, 16]
OE LOW to Output Valid
OE LOW to Output Low-Z[14, 15, 16]
OE HIGH to Output High-Z[14, 15, 16]
4.0
4.5
ns
2.0
2.0
ns
0
0
ns
4.0
4.5
ns
4.5
4.5
ns
0
0
ns
4.0
4.5
ns
tAS
Address Set-up before CLK Rise
1.5
1.5
ns
tADS
ADSC, ADSP Set-up before CLK Rise
1.5
1.5
ns
tADVS
ADV Set-up before CLK Rise
1.5
1.5
ns
tWES
tDS
GW, BWE, BW[A:B] Set-up before CLK Rise
1.5
1.5
ns
Data Input Set-up before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Set-Up before CLK Rise
1.5
1.5
ns
Hold Times
tAH
Address Hold after CLK Rise
0.5
0.5
ns
tADH
ADSP , ADSC Hold after CLK Rise
0.5
0.5
ns
tADVH
ADV Hold after CLK Rise
0.5
0.5
ns
tWEH
tDH
GW,BWE, BW[A:B] Hold after CLK Rise
0.5
0.5
ns
Data Input Hold after CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
0.5
ns
Notes:
11. Timing reference level is 1.5V when VDDQ = 3.3V.
12. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
can be initiated.
14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document #: 38-05424 Rev. **
Page 9 of 15
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