CY7C1361A 查看數據表（PDF） - Cypress Semiconductor
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CY7C1361A Datasheet PDF : 26 Pages
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CY7C1361A
CY7C1363A
256K × 36 Pin Descriptions (continued)
X36 PBGA Pins
X36 QFP Pins
(a) 6P, 7P, 7N, 6N, 6M, (a) 51, 52, 53, 56,
6L, 7L, 6K, 7K, 57, 58, 59, 62, 63
(b) 7H, 6H, 7G, 6G, 6F, (b) 68, 69, 72, 73,
6E, 7E, 7D, 6D, 74, 75, 78, 79, 80
(c) 2D, 1D, 1E, 2E, 2F, (c) 1, 2, 3, 6, 7, 8, 9,
1G, 2G, 1H, 2H,
12, 13
(d) 1K, 2K, 1L, 2L, 2M, (d) 18, 19, 22, 23,
1N, 2N, 1P, 2P 24, 25, 28, 29, 30
2U
38
3U
39
4U
43
for BG and AJ
version
5U
42
for BG and AJ
version
4C, 2J, 4J, 6J, 4R
15, 41, 65, 91
3D, 5D, 3E, 5E, 3F, 5F, 5, 10, 17, 21, 26,
3H, 5H, 3K, 5K, 3M, 40, 55, 60, 67, 71,
5M, 3N, 5N, 3P, 5P
76, 90
1A, 7A, 1F, 7F, 1J, 7J, 4, 11, 20, 27, 54,
1M, 7M, 1U, 7U
61, 70, 77
1B, 7B, 1C, 7C, 4D, 3J,
14, 16, 66
5J, 4L, 1R, 5R, 7R, 1T, 38, 39, 42 for A
2T, 6T, 6U
version
Pin
Name
DQa
DQb
DQc
DQd
TMS
TDI
TCK
TDO
VCC
VSS
VCCQ
NC
Type
Input/
Output
Pin Description
Data Inputs/Outputs: First Byte is DQa. Second Byte is
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data
must meet set-up and hold times around the rising edge
of CLK.
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. Not
available for A package version.
Output
IEEE 1149.1 Test Output: LVTTL-level output. Not
available for A package version.
Power Supply Core Power Supply: +3.3V – 5% and +10%
Ground Ground: GND.
I/O Power
Supply
–
Power Supply for the I/O circuitry
No Connect: These signals are not internally connected.
User can leave it floating or connect it to VCC or VSS.
512K × 18 Pin Descriptions
X18 PBGA Pins
X18 QFP Pins
4P
37
4N
36
2A, 3A, 5A, 6A, 3B, 35, 34, 33, 32, 100,
5B, 6B, 2C, 3C, 5C, 99, 82, 81, 80, 48,
6C, 2R, 6R, 2T, 3T, 5T, 47, 46, 45, 44, 49,
6T
50
92 (AJ Version)
43 (A Version)
5L
93
3G
94
Pin
Name
A0
A1
A
BWa
BWb
4M
87
BWE
4H
88
GW
4K
89
CLK
4E
98
CE
Type
Input-
Synchronous
Pin Description
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Byte Write Enables: A byte Write enable is LOW for a
Write cycle and HIGH for a Read cycle. BWa controls DQa.
BWb controls DQb. Data I/O are high impedance if either
of these inputs are LOW, conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit
Write to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising
edge of CLK.
Clock: This signal registers the addresses, data, chip
enables, Write control and burst control inputs on its rising
edge. All synchronous inputs must meet set-up and hold
times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
Document #: 38-05259 Rev. *A
Page 6 of 26
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