CY7C1361C-133AJXC(2006) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1361C-133AJXC
(Rev.:2006)

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Cypress Semiconductor 

CY7C1361C

CY7C1363C

Logic Block Diagram – CY7C1361C (256K x 36)

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BWD

BWC

BWB

BWA

BWE

GW

CE1

CE2

CE3

OE

ADDRESS

REGISTER

A[1:0]

BURST Q1

COUNTER

AND LOGIC

CLR

Q0

DQD, DQPD

BYTE

WRITE REGISTER

DQC, DQPC

BYTE

WRITE REGISTER

DQB, DQPB

BYTE

WRITE REGISTER

DQA, DQPA

BYTE

WRITE REGISTER

ENABLE

REGISTER

ZZ

SLEEP

CONTROL

Logic Block Diagram – CY7C1363C (512K x 18)

A0,A1,A

MODE

ADV

CLK

ADSC

ADSP

BWB

ADDRESS

REGISTER

A[1:0]

BURST Q1

COUNTER AND

LOGIC

CLR

Q0

DQB,DQPB

WRITE REGISTER

DQA,DQPA

BWA

WRITE REGISTER

BWE

GW

CE1

CE2

ENABLE

REGISTER

CE3

OE

DQD, DQPD

BYTE

WRITE REGISTER

DQC, DQPC

BYTE

WRITE REGISTER

DQB, DQPB

BYTE

WRITE REGISTER

DQA, DQPA

BYTE

WRITE REGISTER

DQB,DQPB

WRITE DRIVER

DQA,DQPA

WRITE DRIVER

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

BUFFERS

DQs

DQPA

DQPB

DQPC

DQPD

INPUT

REGISTERS

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

BUFFERS

DQs

DQPA

DQPB

INPUT

REGISTERS

ZZ

SLEEP

CONTROL

Document #: 38-05541 Rev. *F

Page 2 of 31

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