CY7C1361C 查看數據表（PDF） - Cypress Semiconductor
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CY7C1361C Datasheet PDF : 30 Pages
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PRELIMINARY
CY7C1361C
CY7C1363C
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Truth Table [ 3, 4, 5, 6, 7]
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
35
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Cycle Description
Address
Used CE1 CE2 CE3 ZZ
Deselected Cycle, Power-down None H X X L
ADSP
X
ADSC ADV WRITE OE CLK
DQ
L
X
X X L-H three-state
Deselected Cycle, Power-down None L L X L
L
X
X
X X L-H three-state
Deselected Cycle, Power-down None L X H L
L
X
X
X X L-H three-state
Deselected Cycle, Power-down None L L X L
H
L
X
X X L-H three-state
Deselected Cycle, Power-down None X X X L
H
L
X
X X L-H three-state
Sleep Mode, Power-down
None X X X H
X
X
X
X X X three-state
Read Cycle, Begin Burst
External L H L L
L
Read Cycle, Begin Burst
External L H L L
L
Write Cycle, Begin Burst
External L H L L
H
Read Cycle, Begin Burst
External L H L L
H
Read Cycle, Begin Burst
External L H L L
H
Read Cycle, Continue Burst
Next X X X L
H
Read Cycle, Continue Burst
Next X X X L
H
Read Cycle, Continue Burst
Next H X X L
X
X
X
X
L L-H
Q
X
X
X H L-H three-state
L
X
L
X L-H
D
L
X
H
L L-H
Q
L
X
H H L-H three-state
H
L
H
L L-H
Q
H
L
H H L-H three-state
H
L
H
L L-H
Q
Read Cycle, Continue Burst
Next H X X L
X
H
L
H H L-H three-state
Write Cycle, Continue Burst
Next X X X L
H
H
L
L
X L-H
D
Write Cycle, Continue Burst
Next H X X L
X
H
L
L
X L-H
D
Read Cycle, Suspend Burst Current X X X L
H
H
H
H L L-H
Q
Read Cycle, Suspend Burst Current X X X L
H
H
H
H H L-H three-state
Read Cycle, Suspend Burst Current H X X L
X
H
H
H L L-H
Q
Read Cycle, Suspend Burst Current H X X L
X
H
H
H H L-H three-state
Write Cycle, Suspend Burst Current X X X L
H
H
H
L
X L-H
D
Write Cycle, Suspend Burst Current H X X L
X
H
H
L
X L-H
D
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't
care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05541 Rev. *A
Page 10 of 30
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