HM62256BLFP-4SLT 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HM62256BLFP-4SLT

32,768-word × 8-bit High Speed CMOS Static RAM

Hitachi -> Renesas Electronics 

HM62256B Series

Write Cycle

HM62256B

-4

-5

-7

-8

Parameter

Symbol Min Max Min Max Min Max Min Max Unit Notes

Write cycle time

t WC

45 — 55 — 70 — 85 — ns

Chip selection to end of write

t CW

35 — 40 — 60 — 75 — ns 4

Address setup time

t AS

0 — 0 — 0 — 0 — ns 5

Address valid to end of write

t AW

35 — 40 — 60 — 75 — ns

Write pulse width

t WP

30 — 35 — 50 — 55 — ns 3, 8

Write recovery time

t WR

0 — 0 — 0 — 0 — ns 6

WE to output in high-Z

t WHZ

0 20 0 20 0 25 0 40 ns 1, 2, 7

Data to write time overlap

t DW

20 — 25 — 30 — 35 — ns

Data hold from write time

t DH

0 — 0 — 0 — 0 — ns

Output active from end of write tOW

5 — 5 — 5 — 5 — ns 2

Output disable to output in high-Z tOHZ

0 20 0 20 0 25 0 40 ns 1, 2, 7

Notes: 1. tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later

transition of CS going low or WE going low. A write ends at the earlier transition of CS going

high or WE going high. tWP is measured from the beginning of write to the end of write.

4. tCW is measured from CS going low to the end of write.

5. tAS is measured from the address valid to the beginning of write.

6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.

7. Durng this period, I/O pins are in the output state so that the input signals of the opposite

phase to the outputs must not be applied.

8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem

of data bus contention, tWP ≥ tWHZ max + tDW min.

10

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