CY7C198 查看數據表（PDF） - Cypress Semiconductor
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CY7C198 Datasheet PDF : 9 Pages
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7Rce1v9is8io: n1:0F/2e5b/r8u9ary 29, 1996
CY7C198
AC Test Loads and Waveforms[20]
5V
R1 481W
5V
OUTPUT
OUTPUT
R1 481W
30 pF
INCJLSIUGCDAOINNPGDE
R2525W
(a)
5 pF
R2525W
INCJLSIUGCDAOINNPGDE (b)
C198Ć5
Equivalent toO:UTPUTTHÉVENIN1E67QWUIVALENT1.73V
Switching Characteristics Over the Operating Range[17, 21]
3.0V
GND 10%
< fr
ALL INPUT PULSES
90%
90%
10%
< tr
C198Ć6
7C198-15 7C198-20 7C198-25 7C198-35 7C198-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
tAA
Address to Data Valid
15
tOHA Data Hold from Address Change 3
tACE
CE LOW to Data Valid
15
tDOE
OE LOW to Data Valid
7
tLZOE OE LOW to Low Z[22]
0
tHZOE OE HIGH to High Z[22, 23]
7
tLZCE
CE LOW to Low Z[22]
3
tHZCE CE HIGH to High Z[22, 23]
7
tPU
CE LOW to PowerĆUp
0
tPD
CE HIGH to PowerĆDown
15
WRITE CYCLE[24, 25]
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address SetĆUp to Write End
tHA
Address Hold from Write End
tSA
Address SetĆUp to Write Start
tPWE
WE Pulse Width
tSD
Data SetĆUp to Write End
tHD
Data Hold from Write End
tHZWE WE LOW to High Z[23]
tLZWE WE HIGH to Low Z[22]
Shaded area contains preliminary information.
15
10
10
0
0
9
9
0
7
3
N20otetssrl:owe3r nspsefeodrst.he 15Ćns and 20Ćns speeds, tr 5 ns for the 20Ćns and
21. Test conditions assume signal transition time of 3 ns or less for the
12Ćns and15Ćns speeds and 5 ns for the 20Ćns andslowerspeeds,timing
reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loadĆ
ing of the specified IOL/IOH and 30ĆpF load capacitance.
22. AtgLitvZeaCnnEyd, tegHvivZiceOen.EtiesmlepsesrtahtaunretLaZnOdE,vaonltdagtHeZcWonEdiistiloesns,tthHaZnCtELZiWs lEesfsorthaanny
20
25
35
45
ns
20
25
35
45 ns
3
3
3
3
ns
20
25
35
45 ns
9
10
16
16 ns
0
3
3
3
ns
9
11
15
15 ns
3
3
3
3
ns
9
11
15
15 ns
0
0
0
0
ns
20
20
20
25 ns
20
25
35
45
ns
15
20
22
22
ns
15
20
30
40
ns
0
0
0
0
ns
0
0
0
0
ns
15
20
22
22
ns
10
15
15
15
ns
0
0
0
0
ns
10
11
15
15 ns
3
3
3
3
ns
23. toHfZAOCET,etHstZLCoEa,dasn.dTrtaHnZsWitiEoanries smpeeacsifuiereddw±it5h0C0Lm=V5frpoFmassteinadpyaĆrstta(bte)
voltage.
24. The internal write time of the memory is defined by the overlap of CE
LeiOthWerasingdnWal cEaLnOteWrm. Binoatthesaigwnraitles mbyugsot binegLHOIWGHto. TinhiteiadtaetaaiwnrpiutetasentdĆ
uthpaatntedrhmoilndattimesinthgeshworuitled. be referenced to the rising edge of the signal
25. TLOheWm)inisimthuemsuwmritoefctyHcZleWtEimaenfdortSwDr.ite cycle #3 (WE controlled, OE
4
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