CY7C199C-15VIT 查看數據表（PDF） - Cypress Semiconductor
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CY7C199C-15VIT Datasheet PDF : 13 Pages
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AC Test Conditions
Parameter
C1
C2
R1
R2
RTH
VTH
Description
Capacitor 1
Capacitor 2
Resistor 1
Resistor 2
Resistor Thevenin
Voltage Thevenin
AC Electrical Characteristics[5, 6, 7]
Parameter
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Addres Change
CE to Data Valid
OE to Data Valid
OE to Low Z
OE to High Z
CE to Low Z
CE to High Z
CE to Power-up
CE to Power-down
Write Cycle Time
CE to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
12 ns
Min
Max
12
12
3
12
5
0
5
3
5
0
12
12
9
9
0
0
8
8
0
7
3
CY7C199C
Nom.
Unit
30
pF
5
480
Ω
255
167
1.73
V
15 ns
Min
Max
15
15
3
15
7
0
7
3
7
0
15
15
10
10
0
0
9
9
0
7
3
20 ns
Min
Max Unit
20
ns
20
ns
3
ns
20
ns
9
ns
0
ns
9
ns
3
ns
9
ns
0
ns
20
ns
20
ns
15
ns
15
ns
0
ns
0
ns
15
ns
10
ns
0
ns
10
ns
3
ns
Notes:
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write.
7. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage.
Document #: 38-05408 Rev. *C
Page 5 of 13
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