CY7C261-20JC 查看數據表（PDF） - Cypress Semiconductor
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CY7C261-20JC Datasheet PDF : 16 Pages
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Switching Waveforms[4]
VCC
SUPPLY
CURRENT
A0 - A12
ADDRESS
CS
tAA
O0 - O7
tPD
50%
tHZCS
CY7C261
CY7C263/CY7C264
tPU
50%
tACS
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase
the devices in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended pe-
riods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV inten-
sity multiplied by exposure time) of 25 Wsec/cm2. For an ultra-
violet lamp with a 12 mW/cm2 power rating, the exposure time would
be approximately 35 minutes. The 7C261 or 7C263 needs to
be within 1 inch of the lamp during erasure. Permanent dam-
age may result if the PROM is exposed to high-intensity UV
light for an extended period of time. 7258 Wsec/cm2 is the
recommended maximum dosage.
Operating Modes
Read
Read is the normal operating mode for programmed device. In
this mode, all signals are normal TTL levels. The PROM is
addressed with a 13-bit field, a chip select, (active LOW), is
applied to the CS pin, and the contents of the addressed location
appear on the data out pins.
Program, Program Inhibit, Program Verify
These modes are entered by placing a high voltage VPP on pin
19, with pins 18 and 20 set to VILP. In this state, pin 21 becomes a
latch signal, allowing the upper 5 address bits to be latched into an
onboard register, pin 22 becomes an active LOW program (PGM)
signal and pin 23 becomes an active LOW verify (VFY) signal. Pins
22 and 23 should never be active LOW at the same time. The PRO-
GRAM mode exists when PGM is LOW, and VFY is HIGH. The verify
mode exists when the reverse is true, PGM HIGH and VFY LOW and
the program inhibit mode is entered with both PGM and VFY HIGH.
Program inhibit is specifically provided to allow data to be placed on
and removed from the data pins without conflict
Table 1. Mode Selection
Read or Output Disable A12
A11
A10
Mode
Program
NA
VPP
LATCH
Read
A12
A11
A10
Output Disable
A12
A11
A10
Program
VILP
VPP
VILP
Program Inhibit
VILP
VPP
VILP
Program Verify
VILP
VPP
VILP
Blank Check
VILP
VPP
VILP
Notes:
6. X = “don’t care” but not to exceed VCC ±5%.
7. Addresses A8-A12 must be latched through lines A0-A4 in programming modes.
Pin Function[6, 7]
A9
PGM
A8
VFY
A9
A9
VILP
VIHP
VIHP
VIHP
A8
A8
VIHP
VIHP
VILP
VILP
CS
CS
VIL
VIH
VILP
VILP
VILP
VILP
O7–O0
D7–D0
O7–O0
High Z
D7–D0
High Z
O7–O0
O7–O0
Document #: 38-04010 Rev. **
Page 5 of 16
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