7C408A-15 查看數據表（PDF） - Cypress Semiconductor

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7C408A-15

64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO

Cypress Semiconductor 

CY7C408A

CY7C409A

If data is to be shifted out simultaneously with the data being

shifted in, the concept of “virtual capacity” is introduced. Virtual

capacity is simply how large a packet of data can be shifted in

at a fixed frequency, e.g., 35 MHz, simultaneously with data

being shifted out at any given frequency. Figure 6 is a graph

of packet size[30] vs. shift out frequency (fSOx) for two different

values of shift in frequency (fSIx) when two FIFOs are

cascaded.

The exact complement of this occurs if the FIFOs initially con-

tain data and a high shift out frequency is to be maintained,

i.e.,

ets

a 35

from

MHz fSOx can be sustained

devices cascaded two or

when

three

reading data pack-

deep.[31] If data is

shifted in simultaneously, Figure 6 applies with fSIx and fSOx

interchanged.

400

350

300 fSIx =30MHz

250

200

150

fSIx =35MHz

100

50

0

0 4 8 12 16 20 24 28 32 36

OUTPUT RATE(fSOx) OF BOTTOM FIFO (MHz)

C408A–22

Figure 6. Virtual Capacity vs. Output Rate for Two FIFOs Cascaded Using an Inverter.

Notes:

30. These are typical packet sizes using an inverter whose delay is 4 ns.

31. Only devices with the same speed grade are specified to cascade together.

11

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