CY7C1335-100AC 查看數據表（PDF） - Cypress Semiconductor

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CY7C1335-100AC

32K x 32 Synchronous-Pipelined Cache RAM

Cypress Semiconductor 

PRELIMINARY

CY7C1335

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Ax+1, Ax

Ax+1, Ax

Ax+1, Ax

00

01

10

01

10

11

10

11

00

11

00

01

Fourth

Address

Ax+1, Ax

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

ICCZZ

Snooze mode

standby current

ZZ > VDD − 0.2V

ICCZZ (L Version)

Snooze mode

standby current

ZZ > VDD − 0.2V

tZZS

Device operation to ZZ > VDD − 0.2V

ZZ

tZZREC

ZZ recovery time

ZZ < 0.2V

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ plac-

es the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered

valid nor is the completion of the operation guaranteed. The

device must be deselected prior to entering the “sleep” mode.

CE1 , CE2, CE3, ADSP, and ADSC must remain inactive for the

duration of tZZREC after the ZZ input returns low.

Min

2tCYC

Max

2

500

2tCYC

Unit

mA

µA

ns

ns

5

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