CY7C1335L-100AC 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY7C1335L-100AC

32K x 32 Synchronous-Pipelined Cache RAM

Cypress Semiconductor 

PRELIMINARY

Capacitance[9]

Parameter

CIN

CCLK

CI/O

Description

Input Capacitance

Clock Input Capacitance

Input/Output Capacitance

Test Conditions

TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 3.3V

OUTPUT

Z0 =50Ω

3.3V

OUTPUT

RL =50Ω

5 pF

VL = 1.5V

(a)

INCLUDING

JIG AND

SCOPE

R=317Ω

R=351Ω GND

(b)

1335-2

Notes:

7. Minimum voltage equals -2.0V for pulse durations of less than 20 ns.

8. TA is the “instant on” case temperature.

9. Tested initially and after any design or process changes that may affect these parameters.

10. Input waveform should have a slew rate of 1V/nS.

CY7C1335

Max.

Unit

6

pF

8

pF

8

pF

ALL INPUT PULSES[10]

3.0V

1335-3

9

Share Link: