CY7C421-20JXI 查看數據表（PDF） - Cypress Semiconductor

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CY7C421-20JXI

512 × 9 Asynchronous FIFO

Cypress Semiconductor 

Switching Characteristics

Over the Operating Range

Parameter [6]

tRC

tA

tRR

tPR

tLZR[7]

tDVR[7, 8]

tHZR[7, 8]

tWC

tPW

tHWZ[7]

tWR

tSD

tHD

tMRSC

tPMR

tRMR

tRPW

tWPW

tRTC

tPRT

tRTR

tEFL

tHFH

tFFH

tREF

tRFF

tWEF

tWFF

tWHF

tRHF

tRAE

tRPE

tWAF

tWPF

tXOL

tXOH

Description

Read Cycle Time

Access Time

Read Recovery Time

Read Pulse Width

Read LOW to Low Z

Data Valid after Read HIGH

Read HIGH to High Z

Write Cycle Time

Write Pulse Width

Write HIGH to Low Z

Write Recovery Time

Data Setup Time

Data Hold Time

MR Cycle Time

MR Pulse Width

MR Recovery Time

Read HIGH to MR HIGH

Write HIGH to MR HIGH

Retransmit Cycle Time

Retransmit Pulse Width

Retransmit Recovery Time

MR to EF LOW

MR to HF HIGH

MR to FF HIGH

Read LOW to EF LOW

Read HIGH to FF HIGH

Write HIGH to EF HIGH

Write LOW to FF LOW

Write LOW to HF LOW

Read HIGH to HF HIGH

Effective Read from Write HIGH

Effective Read Pulse Width after EF HIGH

Effective Write from Read HIGH

Effective Write Pulse Width after FF HIGH

Expansion Out LOW Delay from Clock

Expansion Out HIGH Delay from Clock

CY7C421

-15

Min

Max

25

–

–

15

10

–

15

–

3

–

5

–

–

15

25

–

15

–

5

–

10

–

8

–

0

–

25

–

15

–

10

–

15

–

15

–

25

–

15

–

10

–

–

25

–

25

–

25

–

15

–

15

–

15

–

15

–

15

–

15

–

15

15

–

–

15

15

–

–

15

–

15

-20

Min

Max

Unit

30

–

ns

–

20

ns

10

–

ns

20

–

ns

3

–

ns

5

–

ns

–

15

ns

30

–

ns

20

–

ns

5

–

ns

10

–

ns

12

–

ns

0

–

ns

30

–

ns

20

–

ns

10

–

ns

20

–

ns

20

–

ns

30

–

ns

20

–

ns

10

–

ns

–

30

ns

–

30

ns

–

30

ns

–

20

ns

–

20

ns

–

20

ns

–

20

ns

–

20

ns

–

20

ns

–

20

ns

20

–

ns

–

20

ns

20

–

ns

–

20

ns

–

20

ns

Notes

6.

Test conditions

as in part (a) of

assume signal transition time of 3 ns or less, timing

Figure 4 on page 7, unless otherwise specified.

reference

levels

of

1.5

V

and

output

loading

of

the

specified

IOL/IOH

and

30

pF

load

capacitance,

7.

tH1Z0R0trmaVnsfirtoiomn

is measured at +200

the steady state.

mV

from

VOL

and

–200

mV

from

VOH.

tDVR

transition

is

measured

at

the

1.5V

level.

tHWZ

and

tLZR

transition

is

measured

at

8. tHZR and tDVR use capacitance loading as in part (b) of Figure 4 on page 7.

Document Number: 38-06001 Rev. *H

Page 8 of 21

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