CY7C4255V-15(2001) 查看數據表（PDF） - Cypress Semiconductor

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CY7C4255V-15
(Rev.:2001)

32K/64Kx18 Low Voltage Deep Sync FIFOs

Cypress Semiconductor 

CY7C4255V/CY7C4265V

CY7C4275V/CY7C4285V

Switching Waveforms (continued)

Half-Full Flag Timing

WCLK

WEN

HF

RCLK

REN

tCLKH

tCLKL

tENS tENH

tHF

HALF FULL OR LESS

HALF FULL + 1

OR MORE

tHF

tENS

Programmable Almost Empty Flag Timing

tCLKH

WCLK

WEN

[19]

PAE

RCLK

REN

Note:

19. PAE is offset = n. Number of data words into FIFO already = n.

tCLKL

tENS tENH

tPAE

N + 1 WORDS

IN FIFO

tPAE

tENS

HALF FULL OR LESS

4275V–14

n WORDS IN FIFO

4275V–15

Document #: 38-06012 Rev. **

Page 10 of 20

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