CY7C4255V-15(2001) 查看數據表（PDF） - Cypress Semiconductor

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CY7C4255V-15
(Rev.:2001)

32K/64Kx18 Low Voltage Deep Sync FIFOs

Cypress Semiconductor 

CY7C4255V/CY7C4265V

CY7C4275V/CY7C4285V

Switching Waveforms (continued)

Reset Timing [15]

RS

REN, WEN,

LD

EF,PAE

FF,PAF,

HF

Q0 – Q17

tRS

tRSF

tRSF

tRSF

tRSR

First Data Word Latency after Reset with Simultaneous Read and Write

[16]

OE=1

OE=0

4275V–10

WCLK

tDS

D0 –D17

D0 (FIRSTVALID WRITE)

D1

D2

WEN

tENS

RCLK

tFRL[17]

tSKEW2

tREF

EF

D3

D4

REN

Q0 –Q17

OE

tOLZ

tA

tOE

tA[18]

D0

D1

4275V–11

Notes:

15. The clocks (RCLK, WCLK) can be free-running during reset.

16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

17. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2

or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).

18. The first word is always available the cycle after EF goes HIGH.

Document #: 38-06012 Rev. **

Page 8 of 20

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