CY7C4255-15(2004) 查看數據表（PDF） - Cypress Semiconductor

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CY7C4255-15
(Rev.:2004)

8K/16K x 18 Deep Sync FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Reset Timing [17]

RS

REN, WEN,

LD

EF,PAE

FF,PAF,

HF

Q0 – Q17

tRS

tRSF

tRSF

tRSF

tRSR

First Data Word Latency after Reset with Simultaneous Read and Write

CY7C4255

CY7C4265

[18]

OE=1

OE=0

4255–8

WCLK

tDS

D0 –D17

D0 (FIRSTVALID WRITE)

D1

D2

WEN

tENS

RCLK

tFRL[19]

tSKEW2

tREF

EF

D3

D4

REN

Q0 –Q17

OE

tOLZ

tA

tOE

tA[19]

D0

D1

4255–9

Notes:

17. The clocks (RCLK, WCLK) can be free-running during reset.

18. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

19. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK +

tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).

20. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06004 Rev. *B

Page 8 of 22

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