CY7C4255-10AXC(2005) 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY7C4255-10AXC
(Rev.:2005)

8K/16K x 18 Deep Sync FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Reset Timing[16]

RS

REN, WEN,

LD

EF,PAE

FF,PAF,

HF

Q0–Q17

tRS

tRSF

tRSF

tRSF

tRSR

First Data Word Latency after Reset with Simultaneous Read and Write

CY7C4255

CY7C4265

[17]

OE = 1

OE = 0

WCLK

tDS

D0 –D17

D0 (FIRSTVALID WRITE)

D1

D2

WEN

tENS

RCLK

[18]

tFRL

tSKEW2

tREF

EF

D3

D4

REN

Q0 –Q17

OE

tOLZ

tA

tOE

[19]

tA

D0

D1

Notes:

16. The clocks (RCLK, WCLK) can be free-running during reset.

17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

18. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or

tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).

19. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06004 Rev. *C

Page 8 of 22

Share Link: