CY7C4255-35JC 查看數據表（PDF） - Cypress Semiconductor
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CY7C4255-35JC Datasheet PDF : 22 Pages
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Pin Configurations
PLCC
Top View
CY7C4255
CY7C4265
TQFP/STQFP
Top View
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
D14 10
D13 11
D12 12
D11 13
D10 14
D9 15
VCC 16
D8 17
GND 18
D7 19
D6 20
D5 21
D4 22
CY7C4255
CY7C4265
60 VCC/SMODE
59 Q14
D15
1
58 Q13
57 GND
56 Q12
55 Q11
D14
D13
D12
D11
D10
2
3
4
5
6
54 VCC
D9
7
53 Q10
52 Q9
D8
8
D7
9
51 GND
D6
10
50 Q8
D5
11
49 Q7
D4
12
48 VCC
D3
13
D3 23
47 Q6
D2
14
D2 24
46 Q5
D1
15
D1 25
45 GND
D0
16
D0 26
44 Q4
2728 2930 3132 33 34 35 36 37 38 3940 4142 43
4255–2
CY7C4255
CY7C4265
48
Q14
47
Q13
46
GND
45
Q12
44
Q11
43
VCC
42
Q10
41
Q9
40
GND
39
Q8
38
Q7
37
Q6
36
Q5
35
GND
34
Q4
33
VCC
4255–3
Functional Description (continued)
The CY7C4255/65 provides five status pins. These pins are decoded
to determine one of five states: Empty, Almost Empty, Half Full, Al-
most Full, and Full. The Half Full flag shares the WXO pin. This flag
is valid in the stand-alone and width-expansion configurations. In
the depth expansion, this pin provides the expansion out
(WXO) information that is used to signal the next FIFO
when it will be activated.
Selection Guide
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
7C4255/65–10
100
8
10
3
0.5
8
45
50
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
flags become synchronous if the VCC/SMODE is tied to VSS.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
7C4255/65–15
66.7
10
15
4
1
10
45
50
7C4255/65–25
40
15
25
6
1
15
45
50
7C4255/65–35
28.6
20
35
7
2
20
45
50
Density
Package
CY7C4255
8K x 18
64-pin
PLCC, TQFP,
STQFP
CY7C4265
16K x18
64-pin
PLCC, TQFP,
STQFP
2
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