CY7C4255-10AC 查看數據表（PDF） - Cypress Semiconductor

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CY7C4255-10AC

8K/16K x 18 Deep Sync FIFOs

Cypress Semiconductor 

CY7C4255

CY7C4265

Pin Definitions

Signal Name Description I/O

Function

D0 –17

Q0–17

WEN

REN

WCLK

Data Inputs

Data Outputs

Write Enable

Read Enable

Write Clock

I Data inputs for an 18-bit bus.

O Data outputs for an 18-bit bus.

I Enables the WCLK inpu.t

I Enables the RCLK input.

I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not

Full. When LD is asserted, WCLK writes data into the programmable flag-offset

register.

RCLK

WXO/HF

EF

FF

PAE

PAF

LD

FL/RT

WXI

RXI

RXO

Read Clock

I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not

Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-

set register.

Write Expansion O Dual-Mode Pin:

Out/Half Full Flag

Single device or width expansion – Half Full status flag.

Cascaded – Write Expansion Out signal, connected to WXI of next device.

Empty Flag

O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

Full Flag

O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

Programmable

Almost Empty

Programmable

Almost Full

Load

O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset

value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied

to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS.

O When PAF is LOW, the FIFO is almost full based on the almost full offset value

programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to

VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS.

I When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the programma-

ble-flag-offset register.

First Load/

Retransmit

I Dual-Mode Pin:

Cascaded – The first device in the daisy chain will have FL tied to VSS; all other

devices will have FL tied to VCC. In standard mode or width expansion, FL is tied

to VSS on all devices.

Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone

mode by strobing RT.

Write Expansion

Input

Read Expansion

Input

Read Expansion

Output

I Cascaded – Connected to WXO of previous device.

Not Cascaded – Tied to VSS.

I Cascaded – Connected to RXO of previous device.

Not Cascaded – Tied to VSS.

O Cascaded – Connected to RXI of next device.

RS

Reset

OE

Output Enable

VCC/SMODE Synchronous

Almost Empty/

Almost Full Flags

I Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

I When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-

nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

I Dual-Mode Pin:

Asynchronous Almost Empty/Almost Full flags – tied to VCC.

Synchronous Almost Empty/Almost Full flags – tied to VSS.

(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)

3

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