CY7C4255-35JC 查看數據表（PDF） - Cypress Semiconductor
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CY7C4255-35JC Datasheet PDF : 22 Pages
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CY7C4255
CY7C4265
AC Test Loads and Waveforms[9, 10]
5V
OUTPUT
R1 1.1 KΩ
CL
INCLUDING
JIG AND
SCOPE
R2
680Ω
4255–4
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
410Ω
1.91V
4255–5
Switching Characteristics Over the Operating Range
7C42X5–10 7C42X5–15 7C42X5–25 7C42X5–35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tS
Clock Cycle Frequency
100
66.7
40
28.6 MHz
tA
Data Access Time
2
8
2 10 2 15 2 20 ns
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
3
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set-Up Time
3
4
6
7
ns
tENH
tRS
Enable Hold Time
Reset Pulse Width[11]
0.5
1
1
2
ns
10
15
25
35
ns
tRSR
Reset Recovery Time
8
10
15
20
ns
tRSF
Reset to Flag and Output Time
10
15
25
35 ns
tPRT
Retransmit Pulse Width
30
35
45
55
ns
tRTR
tOLZ
Retransmit Recovery Time
Output Enable to Output in Low Z[12]
60
65
75
85
ns
0
0
0
0
ns
tOE
tOHZ
Output Enable to Output Valid
Output Enable to Output in High Z[12]
3
7
3
8
3 12 3 15 ns
3
7
3
8
3 12 3 15 ns
tWFF
Write Clock to Full Flag
8
10
15
20 ns
tREF
Read Clock to Empty Flag
8
10
15
20 ns
tPAFasynch Clock to Programmable Almost-Full Flag[13]
12
16
20
25 ns
(Asynchronous mode, VCC/SMODE tied to VCC)
tPAFsynch
Clock to Programmable Almost-Full Flag
8
(Synchronous mode, VCC/SMODE tied to VSS)
10
15
20 ns
tPAEasynch Clock to Programmable Almost-Empty Flag[13]
12
16
20
25 ns
(Asynchronous mode, VCC/SMODE tied to VCC)
Notes:
9. CL = 30 pF for all AC parameters except for tOHZ.
10. CL = 5 pF for tOHZ.
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
5
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