CY62256V 查看數據表（PDF） - Cypress Semiconductor
零件编号
产品描述 (功能)
生产厂家
CY62256V Datasheet PDF : 12 Pages
| |||
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
CY62256V
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
CE
OE
DATA OUT
VCC
SUPPLY
CURRENT
t RC
tACE
tDOE
t LZOE
HIGH IMPEDANCE
tLZCE
t PU
50%
DATA VALID
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC
ADDRESS
CE
tAW
tSA
WE
t PWE
t HZOE
tHZCE
HIGH
IMPEDANCE
t PD
ICC
50%
ISB
tHA
OE
DATA I/O
NOTE 17
t HZOE
tSD
DATAINVALID
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05057 Rev. *F
tHD
Page 6 of 12
[+] Feedback
Share Link: 