CY7C63001C 查看數據表（PDF） - Cypress Semiconductor
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CY7C63001C Datasheet PDF : 28 Pages
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CY7C63001C
CY7C63101C
Figure 6-4. Reading the register returns the value of the Cext
pin. During a reset, the Cext pin is HIGH.
b7
b6
b5
b4
Reserved
Reserved
Reserved
Reserved
b3
Reserved
b2
Reserved
b1
Reserved
0
0
0
0
0
0
0
Figure 6-4. The Cext Register (Address 0x22)
b0
CEXT
R/W
1
6.5 On-Chip Timer
The USB Controller is equipped with a free-running timer
driven by a clock one-sixth the resonator frequency. Bits 0
through 7 of the counter are readable from the read-only Timer
Register located at I/O address 0x23. The Timer Register is
cleared during a Power-On Reset and whenever Suspend
mode is entered. Figure 6-5 illustrates the format of this
register and Figure 6-6 is its block diagram.
With a 6 MHz resonator, the timer resolution is 1 µs.
The timer generates two interrupts: the 128-µs interrupt and
the 1.024-ms interrupt.
b7
b6
b5
b4
b3
b2
b1
b0
T.7
T.6
T.5
T.4
T.3
T.2
T.1
T.0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Figure 6-5. Timer Register (Address 0x23)
1.024-ms interrupt
128-µs interrupt
9
8
7
6
54
32
1
0
Resonator Clock/6
Figure 6-6. Timer Block Diagram
8
To Timer Register
Document #: 38-08026 Rev. *B
Page 8 of 28
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