CY7C955 查看數據表（PDF） - Cypress Semiconductor
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CY7C955 Datasheet PDF : 78 Pages
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PRELIMINARY
CY7C955
(LOF) is declared when the OOF condition fails to clear within
3 ms. LOF clears after 3 ms of frames with valid framing char-
acters.
Receive SONET Section Overhead Processor (RSOP)
The RSOP provides descrambling, SONET section alarm in-
dication, and error monitoring.
The data is descrambled using the generating polynomial 1 +
x6 + x7. The A1, A2, and C1 bytes are not descrambled. The
scrambling process may be disabled under register control.
The BIP−8 value calculated over the previous scrambled frame
is compared with the B1 byte of the current frame section over-
head after descrambling. If the two values do not match, the
B1PAR output is taken HIGH. Up to 64,000 errors can be de-
tected per second (8000 frames/second * 8 bit-errors
(max)/frame). Errors are recorded in a 16-bit saturating
counter that can be read through the controller interface.
Receive SONET Line Overhead Processor (RLOP)
The RLOP provides SONET line alarm indications and error
monitoring.
A Line Alarm Indication Signal (LAIS) is asserted when a 111
pattern is detected for five consecutive frames in bits 6,7, and
8 of the first K2 byte of the Automatic Protection Switching
channel. LAIS is removed when anything other than a 111 pat-
tern is received for five consecutive frames.
A Line Far End Receive Failure (LFERF) or Line RDI is indi-
cated with a 110 pattern is detected for five consecutive frames
in bits 6,7, and 8 of the first K2 byte. LFERF is removed when
anything other than a 110 pattern is received for five consec-
utive frames.
The BIP−24 (BIP−8 for STS−1 RATE) value calculated over the
previous line overhead and SPE is compared with the B2 bytes
of current frame. Up to 192,000 errors can be detected per
second (3 channels/frame * 8 errors (max)/channel * 8000
frames/second). Errors are recorded in a 20-bit saturating
counter that can be read through the controller interface.
Far End Block Errors (FEBE) are detected by examining the
value in the third Z2 byte. This value (0−18h) is added to the
count in an 18-bit saturating counter that can be read through
the controller interface.
Receive SONET Path Overhead Processor (RPOP)
The RPOP provides pointer interpretation, SPE extraction,
SONET path alarm indications, and error monitoring.
The payload location is determined by examining the values in
the H1 and H2 bytes of the line overhead which indicate the J1
byte of the SPE. The RPOP can process a J1 byte located
anywhere in the SPE. Loss of Pointer (LOP) is set when a valid
pointer value has not been found within eight consecutive
frames. This register bit is cleared when a valid pointer is found
for three consecutive frames. Path Alarm Indication Signal
(PAIS) (Reg30H, bit 3) is set when the H1 and H2 bytes are
set to all ones for 3 consecutive frames. This register bit is
cleared when a valid pointer is found for three consecutive
frames. PAIS does not cause LOP to be set. The SPE location
is provided to the Receive ATM Cell Processor for cell extrac-
tion.
The BIP−8 value calculated over the previous SPE is com-
pared with the B3 byte of the current path overhead. Up to
65,535 errors can be detected per second. Errors are recorded
in a 16-bit saturating counter that can be read through the
controller interface.
Path Far End Block Errors (PFEBE) are detected by examining
the value in bits 1 through 4 of G1. This value (0−8h) is added
to the count in a 16-bit saturating counter that can be read
through the controller interface.
Path Far End Receive Failures (PFERF) are detected by ex-
amining the value in bits 1 through 4 of G1. If this value is 9h
for two consecutive frames, PFERF is set. This register bit is
cleared when anything other than 9h appears for two consec-
utive frames.
Path Remote Defect Indication (Path RDI) is detected by ex-
amining bit 5 of G1. If this value is 1h for 5 consecutive frames,
PYEL is set. This register bit is cleared when a 0 appears in
bit 5 for 5 consecutive frames.
Receive ATM Cell Processor (RACP)
The RACP block provides cell delineation, HEC checking and
correcting, cell filtering for idle/unassigned cells, cell payload
descrambling, status indications, and error monitoring.
Cell delineation is performed by comparing the HEC sequence
calculated over the first four bytes of the SPE to the fifth byte.
If these values match, cell boundary has been determined. If
not, the calculation advances one byte further into the payload
(bytes 2−5) and the check is performed again. The HEC se-
quence is a CRC−8 calculated over the first 4 octets of the ATM
cell header using the polynomial x8 + x2 + x + 1. The coset x6
+ x4 + x2 + 1 is added (modulo 2) to the residue before com-
parison with the received sequence. This is the HUNT state of
the cell delineation process. When a valid match has occurred
the process enters the PRESYNC state. When 7 consecutive
matches occur the process enters the SYNC state. If 6 con-
secutive incorrect HEC matches are detected the process
moves back to the HUNT state. The average time for cell de-
lineation is 93µs for STS−1 and 31µs for STS−3C.
The HEC sequence is used not only to check for cell align-
ment, but also to insure that integrity of the ATM header. The
HEC is used to correct single bit errors and to detect multiple
bit errors. This feature can be disabled. The register file con-
tains two saturating 8-bit counters for HEC errors; one for cells
with single bit errors and another for multiple-bit errors. Cells
with multiple bit errors are optionally discarded. Figure 3
shows the state diagram for HEC.
The RACP optionally discards Idle/Unassigned cells. These
cells contain a VPI/VCI address of 0h. Also, a Header Mask
and Header Match register are provided to allow cells with a
particular header characteristic in GFC, PTI and CLP to be
filtered.
The payload of valid cells are descrambled using the polyno-
mial x43 +1. The cell headers are not descrambled since they
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