CY8C27466 查看數據表（PDF） - Cypress Semiconductor
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CY8C27466 Datasheet PDF : 39 Pages
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1. Pin Information
This chapter describes, lists, and illustrates the CY8C27x66 PSoC device pins and pinout configurations.
1.1 Pinouts
The CY8C27x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.1 28-Pin Part Pinout
Table 1-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
Type
Pin
No. Digital Analog Name
Description
1
IO
I
P0[7] Analog column mux input.
2
IO
IO P0[5] Analog column mux input and column output.
3
IO
IO P0[3] Analog column mux input and column output.
4
IO
I
P0[1] Analog column mux input.
5
IO
P2[7]
6
IO
P2[5]
7
IO
I
P2[3] Direct switched capacitor block input.
8
IO
I
P2[1] Direct switched capacitor block input.
9
Power
SMP Switch Mode Pump (SMP) connection to
external components required.
10
IO
P1[7] I2C Serial Clock (SCL)
11
IO
P1[5] I2C Serial Data (SDA)
12
IO
P1[3]
13
IO
P1[1] Crystal (XTALin), I2C Serial Clock (SCL)
14
Power
Vss
Ground connection.
15
IO
P1[0] Crystal (XTALout), I2C Serial Data (SDA)
16
IO
P1[2]
17
IO
P1[4] Optional External Clock Input (EXTCLK)
18
IO
P1[6]
19
Input
XRES Active high pin reset with internal pull down.
20
IO
I
P2[0] Direct switched capacitor block input.
21
IO
I
P2[2] Direct switched capacitor block input.
22
IO
P2[4] External Analog Ground (AGND)
23
IO
P2[6] External Voltage Reference (VREF)
24
IO
I
P0[0] Analog column mux input.
25
IO
IO P0[2] Analog column mux input and column output.
26
IO
IO P0[4] Analog column mux input and column output.
27
IO
I
P0[6] Analog column mux input.
28
Power
Vdd
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
CY8C27466 28-Pin PSoC Device
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
28
2
27
3
26
4
25
5
24
6 PDIP 23
7 SSOP 22
8
9
SOIC
21
20
10
19
11
18
12
17
13
16
14
15
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], External VREF
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
May 2004
Document No. 38-12019 Rev. *B
8
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