CY8C5246LTI-029(2011_03) 查看數據表（PDF） - Cypress Semiconductor
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CY8C5246LTI-029 Datasheet PDF : 94 Pages
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PRELIMINARY
PSoC® 5: CY8C52 Family Datasheet
PSoC uses a JTAG (4 wire) or SWD (2 wire) interface for
programming, debug, and test. Using these standard interfaces
enables the designer to debug or program the PSoC with a
variety of hardware solutions from Cypress or third party
vendors. The Cortex-M3 debug and trace modules include FPB,
DWT, ETM, and ITM. These modules have many features to help
solve difficult debug and trace problems. Details of the
programming, test, and debugging interfaces are discussed in
the “Programming, Debug Interfaces, Resources” section on
page 49 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1 and
Figure 2-2. Using the Vddio pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each Vddio may sink up to 100 mA total to its
associated I/O pins. On the 68-pin and 100-pin devices each set
of Vddio associated pins may sink up to 100 mA. The 48 pin
device may sink up to 100 mA total for all Vddio0 plus Vddio2
associated I/O pins and 100 mA total for all Vddio1 plus Vddio3
associated I/O pins.
Figure 2-1. 68-pin QFN Part Pinout[3]
(TRACEDATA[2], GPIO) P2[6] 1
(TRACEDATA[3], GPIO) P2[7] 2
(SIO) P12[4] 3
(SIO) P12[5] 4
Vssb 5
Ind 6
Vboost 7
Vbat 8
Vssd 9
XRES 10
(TMS, SWDIO) P1[0] 11
(TCK, SWDCK) P1[1] 12
(GPIO) P1[2] 13
(TDO, GPIO) P1[3] 14
(TDI, GPIO) P1[4] 15
(GPIO) P1[5] 16
Vddio1 17
Lines show Vddio
to I/O supply
association
QFN
(Top View)
51 P0[3] (GPIO, OpAmp0-/Extref0)
50 P0[2] (GPIO, OpAmp0+)
49 P0[1] (GPIO, OpAmp0out)
48 P0[0] (GPIO, OpAmp2out)
47 P12[3] (SIO)
46 P12[2] (SIO)
45 Vssd
44 Vdda
43 Vssa
42 Vcca
41 P15[3] (GPIO, kHz XTAL: Xi)
40 P15[2] (GPIO, kHz XTAL: Xo)
39 P12[1] (SIO)
38 P12[0] (SIO)
37 P3[7] (GPIO, OpAmp3out)
36 P3[6] (GPIO, OpAmp1out)
35 Vddio3
Notes
3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-66236 Rev. **
Page 5 of 94
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